The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, it relates to a semiconductor device including a high dielectric constant film as a gate insulating film and a method for fabricating the same.
In a CMOS (complementary metal-oxide semiconductor) device having been developed to be more and more refined, when a conventionally used gate insulating film made of a silicon oxide film or the like is reduced in the thickness, the leakage current is increased so as to increase the standby current of an LSI (large scale integration) circuit including the device. Therefore, the thickness of a gate insulating film made of a silicon oxide film or the like has been reduced to its limit. Accordingly, examinations are now being earnestly made for application to a gate insulating film of a high dielectric constant film, which can attain a small electric thickness even when the physical thickness is large. Currently, HfSiON is regarded as the most promising material for a high dielectric constant film used as a gate insulating film. Also, in a polysilicon electrode conventionally used as a gate electrode, it has become impossible to ignore the depletion, and hence, a metal gate electrode free from depletion is now being earnestly studied.
As CMOS process using such a HfSiON gate insulating film and a metal gate electrode, use of a polysilicon electrode in an N-type MOSFET (metal-oxide-semiconductor field-effect transistor) and a TiN metal electrode in a P-type MOSFET has been proposed as described in Non-patent Document 1 (T. Hayashi, et al., Cost Worthy and High Performance LSTP CMIS: Poly-Si/HfSiON nMIS and Poly-Si/TiN/HfSiON pMIS, IEDM Tech. Dig., 2006, pp. 247-250).
A method for fabricating this conventional semiconductor device will now be described with reference to cross-sectional views of FIGS. 11A through 11C showing respective procedures in the method.
First, as shown in FIG. 11A, an isolation region 111 is formed in a semiconductor substrate 110 so as to isolate a P-type MOSFET region 101 and an N-type MOSFET region 102. Then, an interface layer 112 of SiON and a HfSiO film 113 are successively formed on the semiconductor substrate 110. Thereafter, the HfSiO film 113 is nitrided so as to form a HfSiON modified layer 115, and subsequently, a TiN film 116 is formed on the HfSiON modified layer 115 by CVD (chemical vapor deposition).
Next, as shown in FIG. 11B, a portion of the TiN film 116 disposed in the N-type MOSFET region 102 is selectively removed, so as to expose the HfSiON modified layer 115 in the N-type MOSFET region 102.
Then, as shown in FIG. 11C, a polysilicon film 120 doped with an N-type impurity is formed over the semiconductor substrate 110, and then, the polysilicon film 120, the TiN film 116, the HfSiON modified layer 115, the HfSiO film 113 and the interface layer 112 are patterned. In this manner, a gate electrode 105 including the TiN film 116 and the polysilicon film 120 is formed in the P-type MOSFET region 101 above the semiconductor substrate 110 with a gate insulating film 103 including the interface layer 112, the HfSiO film 113 and the HfSiON modified layer 115 sandwiched therebetween. Also, a gate electrode 106 including the polysilicon film 120 is formed in the N-type MOSFET region 102 above the semiconductor substrate 110 with a gate insulating film 104 including the interface layer 112, the HfSiO film 113 and the HfSiON modified layer 115 sandwiched therebetween.
Thereafter, although not shown in the drawings, sidewall spacers, source/drain regions and the like are formed by known techniques, so as to complete an N-type MOSFET including the polysilicon electrode (namely, the gate electrode 106) and a P-type MOSFET including the TiN metal electrode (namely, the gate electrode 105).